Hardware Implementation of the GPS authentication

In this paper, we explore new area/throughput trade- offs for the Girault, Poupard and Stern authentication protocol (GPS). This authentication protocol was selected in the NESSIE competition and is even part of the standard ISO/IEC 9798. The originality of our work comes from the fact that we exploit a fixed key to increase the throughput. It leads us to implement GPS using the Chapman constant multiplier. This parallel implementation is 40 times faster but 10 times bigger than the reference serial one. We propose to serialize this multiplier to reduce its area at the cost of lower throughput. Our hybrid Chapman's multiplier is 8 times faster but only twice bigger than the reference. Results presented here allow designers to adapt the performance of GPS authentication to their hardware resources. The complete GPS prover side is also integrated in the network stack of the PowWow sensor which contains an Actel IGLOO AGL250 FPGA as a proof of concept.Comment: ReConFig - International Conference on ReConFigurable Computing and FPGAs (2012

Master Interface for On-Chip Hardware Accelerator Burst Communications

International audienceWe explain a systematic way of interfacing data-flow hardware accelerators (IP) for their integration in a system on chip. We abstract the communication behaviour of the data flow IP so as to provide basis for an interface generator. Then we measure the throughput obtained for different architectures of the interface mechanism by a cycle accurate bit accurate simulation of a SoC integrating a data-flow IP. We show in which configuration the optimal communication scheme can be reached

Efficient on-chip communications for data-flow IPs

International audienceWe explain a systematic way of interfacing data-flow hardware accelerators (IP) for their integration in a system on chip. We abstract the communication behaviour of the data flow IP so as to provide basis for an interface generator. We also explain which parameter this interface generator has to take into account. We validate our interface mechanism by a cycle accurate bit accurate simulation of a SoC integrating a data-flow ip

Cycle Accurate Simulation Model Generation for SoC Prototyping

RR 2004-18, ENS-Lyon, 24 pagesWe present new results concerning the integration of high level designed ips into a complete System on Chip. We first introduce a new compu- tation model that can be used for cycle accurate simulation of register transfer level synthesized hardware. Then we provide simulation of a SoC integrating a data-flow ip synthesized with MMAlpha and the So- cLib cycle accurate simulation environment. This integration also vali- dates an efficient generic interface mechanism for data-flow ips

FPGA-based Implementation of Multiple PHY Layers of IEEE 802.15.4 Targeting SDR Platform

International audienceWhile SDR platforms become more and more accessible to a large community of researchers with affordable prices, open source FPGA-based implementation of wireless communication systems are still not available. This paper presents an open source FPGA-based design of IEEE 802.15.4 PHY Layers developed in the context of a new SDR testbed named FIT/CorteXlab. We propose a VHDL implementation of the three available options of the IEEE 802.15.4 physical layer parametrized and easily reconfigurable. We have validated our design on Nutaq platform which combines Xilinx Virtex-6 FPGA and tunable Radio420x RF transceiver. A tutorial style approach is adopted to describe the multiple PHY Layers of both the baseband TX and RX IPs of IEEE 802.15.4 standard. More focus is given to the symbol timing/carrier recovery and considerations for FPGA implementation are outlined. The IPs presented here will participate to the building of an open source hardware SDR library similar to GNU radio but targeted to FPGA-based platforms.Nous présentons une implémentation FPGA opensource de la couche physique du standard IEEE 802.15.4. Cette implémentation est réalisée dans le cadre de l'équipex FIT/CorteXlab, sur une plateforme Nutaq qui contient un FPGA Xilinx Virtex-6 et un front-end radio flexible Radio420x RF

Advances in Bit Width Selection Methodology

We describe a method for the formal determination of signal bit width in fixed points VLSI implementations of signal processing algorithms containin- g loop nests. The main advance of this paper lies in the fact that we use results of the (max,+) algebraic theory to find the integral bit width of algorithms containing loop nests whose bound parameters are not statically known. Combined with recent results on fractional bit width determination, the results of this paper can be used for 1-dimensional systolic-like arrays implementing linear signal processing algorithms. Although they are presented in the context of a specific high level design methodology (based on systems of affine recurrence equations), the results of this work can be used in many high level design environments

Full Duplex Prototype of OFDM on GNURadio and USRPs

International audienceFull-duplex is a technology in telecommunication domain that can perform transmitting and receiving at the same time and in the same frequency band. The major obstacle of full-duplex is the self-interference (SI). Some previous works have focused on the SI cancellation in radio frequency (RF), and generally on a narrowband signal model. We have implemented a full-duplex prototype with orthogonal frequency-division multiplexing (OFDM) technology on GNURadio and Universal Software Radio Peripherals (USRP). We focus on the baseband, namely the digital part of the SI cancellation. Our testbed can achieve a digital cancellation of 27dB. After the cancellation, the signal of interest can achieve a bit error rate (BER) in the scale of 105 at 4 meters, which is very close to the performance of half-duplex. This is, to our knowledge, the first full duplex implementation for OFDM technology

Compilation for heterogeneous SoCs : bridging the gap between software and target-specific mechanisms

International audienceCurrent applications constraints are pushing for higher computation power while reducing energy consumption, driving the development of increasingly specialized socs. In the mean time, these socs are still programmed in assembly language to make use of their specific hardware mechanisms. The constraints on hardware development bringing specialization, hence heterogeneity, it is essential to support these new mechanisms using high-level programming. In this work, we use a parametric data flow formalism to abstract the application from any hardware platform. From this premise, we propose to contribute to the compilation of target independent programs on heterogeneous platforms. These developments are threefold, with 1) the support of hardware accelerators for computation using actor fusion, 2) the automatic generation of communications on complex memory layouts and 3) the synchronization of distributed cores using hardware mechanisms for scheduling. The code generation is illustrated on a telecommunication dedicated heterogeneous soc

Contrôle d'application flot de données pour les systèmes sur puces : étude de cas sur la plateforme Magali

International audienceLes applications embarquées demandent toujours plus de puissance de calcul pour moins de consommation, avec comme conséquence l'apparition de systèmes sur puces dédiés. Dans le domaine du traitement du signal, le modèle de calcul flot de données est couramment utilisé pour la programmation de ces systèmes sur puce. Il est donc nécessaire d'avoir un modèle d'exécution adapté à ces architectures et répondant aux contraintes applicatives. Dans ce tra- vail, nous proposons un nouveau modèle d'exécution pour le contrôle d'applications flot de données. Notre approche s'appuie sur les liens entre les caractéristiques des applications et les performances selon le modèle d'exécution associé. Ce travail est illustré avec une étude de cas sur la plateforme Magali

Cognitive Radio Programming: Existing Solutions and Open Issues

Software defined radio (sdr) technology has evolved rapidly and is now reaching market maturity, providing solutions for cognitive radio applications. Still, a lot of issues have yet to be studied. In this paper, we highlight the constraints imposed by recent radio protocols and we present current architectures and solutions for programming sdr. We also list the challenges to overcome in order to reach mastery of future cognitive radios systems.La radio logicielle a évolué rapidement pour atteindre la maturité nécessaire pour être mise sur le marché, offrant de nouvelles solutions pour les applications de radio cognitive. Cependant, beaucoup de problèmes restent à étudier. Dans ce papier, nous présentons les contraintes imposées par les nouveaux protocoles radios, les architectures matérielles existantes ainsi que les solutions pour les programmer. De plus, nous listons les difficultés à surmonter pour maitriser les futurs systèmes de radio cognitive